Trách nhiệm chính

Develop and execute verification plans for high-speed mixed-signal PHY IPs, including defining coverage goals, test scenarios, and success criteria.
Perform RTL simulations and gate-level SDF-annotated simulations within UVM-based verification environments.
Build functional tests to stress corner cases, protocol compliance, and power states for PHY IP blocks.
Generate VCD files and perform power analysis using PrimeTime PX to correlate simulation activity with power consumption.
Debug complex verification failures by analyzing waveforms, coverage reports, and simulation logs to isolate root causes.
Collaborate with design, analog, and integration teams to align verification strategies with IP architecture.
Review and refine verification infrastructure to identify coverage gaps and propose new tests.

Yêu cầu công việc

5+ years of hands-on experience in ASIC RTL design flow with a strong focus on verification and debugging.
Demonstrated expertise in RTL and gate-level simulation, including SDF-annotated GLS.
Proficiency in SystemVerilog and experience working within UVM-based verification environments.
Strong debugging skills including waveform analysis, coverage review, and simulation log interpretation.
Experience with power analysis tools such as PrimeTime PX, including VCD generation.
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.

Yêu cầu ưu tiên

Knowledge of high-speed interface protocols such as DDR PHY, HBM PHY, or UCIe PHY is a strong plus.

Mức lương

Salary range details will be provided by the recruiter during the hiring process.

Phúc lợi

Comprehensive range of health, wellness, and financial benefits provided as part of total rewards.

Hình thức làm việc

Thông tin khác

The team develops high-speed mixed-signal PHY IP for memory interfaces and interconnects in advanced semiconductor products.
Candidates must be comfortable working in English across global teams.

Digital Verification Senior Staff Engineer