Trách nhiệm chính

Develop and validate verification environments for high-bandwidth interface IP from functional specifications through coverage closure.
Write test cases, assertions, and checkers in SystemVerilog to ensure comprehensive functional coverage.
Debug RTL, gate-level, and co-simulations involving real signal modeling for analog mixed-signal designs using VCS and Verdi.
Drive coverage analysis and closure across code, functional, and assertion metrics.
Participate in technical and peer reviews to ensure verification quality and process adherence.
Collaborate with design, architecture, and silicon validation teams to identify and resolve issues early.
Mentor and elevate the skills of the Vietnam engineering team through knowledge sharing.

Yêu cầu công việc

Bachelor's, Master's, or PhD in Electronics Engineering, Electromechanics, Telecommunications, or related field.
2+ years of hands-on design verification experience, ideally on digital or mixed-signal IP.
Strong proficiency with SystemVerilog, UVM, and industry-standard verification methodologies.
Experience with VCS and Verdi for simulation and debug.
Solid understanding of verification planning, coverage-driven verification, and assertion-based verification.
Clear English communication skills for reporting, presenting, and reviewing.

Yêu cầu ưu tiên

Mức lương

Salary range details will be provided by the recruiter during the hiring process.

Phúc lợi

Hình thức làm việc

Thông tin khác

This is a full-time employee role.
The role focuses on verification for high-bandwidth interface IP powering AI, 5G, cloud, and IoT applications.

Design Verification Sr Engineer in Ha Noi