Trách nhiệm chính

Drive complete digital implementation from RTL to GDS for high-speed interface IPs including Serdes, DDR, HDMI, MIPI, and USB at 7nm, 5nm, and 3nm nodes.
Execute synthesis, floorplanning, power planning, clock tree synthesis, placement, routing, and physical verification using Synopsys EDA tools.
Perform static timing analysis and close timing across multiple process corners, voltages, and operating modes.
Run EMIR signoff, analyze IR drop and electromigration, and iterate on power grid design to ensure reliable silicon operation.
Build physical design methodologies and automation scripts using TCL, Python, Perl, and Make to improve efficiency across projects.
Collaborate with RTL designers, verification teams, product engineers, and customers to ensure timely delivery and resolve technical issues.
Provide technical support to customers during IP integration and debug design issues as they arise.

Yêu cầu công việc

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science.
5+ years of hands-on experience in ASIC physical implementation, specifically RTL to GDS flows using industry-standard EDA tools.
Deep understanding of IC design fundamentals, physical implementation flows, and signoff methodologies for deep submicron designs.
Proficiency with industry-standard data formats including Verilog, GDS, LEF, DEF, SDF, LIB, UPF, CPF, and SPEF.
Strong scripting skills in TCL, Python, Perl, Unix Shell, and Make for automation and flow development.
Solid written and verbal communication skills in English for technical documentation and cross-functional collaboration.

Yêu cầu ưu tiên

Experience with Synopsys physical design tools such as Fusion Compiler, IC Compiler II, PrimeTime, or StarRC.

Mức lương

Phúc lợi

Hình thức làm việc

Thông tin khác

Join the Digital Implementation team working on 7nm, 5nm, and 3nm nodes.
Projects support AI accelerators, autonomous vehicle SoCs, 5G infrastructure, high-performance compute, cloud, and IoT applications.

ASIC Physical Design, Staff Engineer