Trách nhiệm chính

Design and develop high-speed mixed-signal PHY IP blocks using SystemVerilog and Verilog.
Author detailed micro-architecture specifications based on industry protocol standards.
Execute RTL design from concept through tape-out while ensuring quality via Linting, CDC checks, and coding standards.
Collaborate with verification engineers to debug RTL and gate-level simulations with SDF timing annotation.
Provide technical support to customers during SoC integration, post-silicon bring-up, and field deployment.
Participate in design reviews and mentor junior engineers on RTL best practices.

Yêu cầu công việc

5+ years of hands-on experience in ASIC RTL design flow, from specification through tape-out.
Strong proficiency in SystemVerilog and Verilog for complex digital design.
Proficiency in scripting languages such as Python, Perl, or Tcl for design automation.
Solid understanding of design quality checks including Linting, CDC analysis, and synthesis constraints.
Strong English communication skills for cross-functional collaboration and customer interaction.

Yêu cầu ưu tiên

Experience with post-silicon debugging and customer support.
Knowledge of high-speed serial protocols, DFT techniques, or UVM verification methodologies.

Mức lương

Phúc lợi

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Thông tin khác

ASIC Digital Design, Sr Staff Engineer