Trách nhiệm chính

Develop and execute verification plans for high-speed mixed-signal PHY IPs including defining coverage goals, test scenarios, and success criteria.
Perform RTL simulations and gate-level SDF-annotated simulations within UVM-based verification environments.
Build functional tests that stress corner cases, protocol compliance, and power states for PHY IP blocks.
Generate VCD files and run power analysis using PrimeTime PX while correlating simulation activity with power consumption.
Debug complex verification failures by analyzing waveforms, coverage reports, and simulation logs to isolate root causes.
Collaborate with design, analog, and integration teams to align verification strategy with IP architecture.
Review and refine verification infrastructure to identify coverage gaps and propose new tests.

Yêu cầu công việc

5+ years of hands-on experience in ASIC RTL design flow with a strong focus on verification and debugging.
Expertise in RTL and gate-level simulation, including SDF-annotated GLS.
Proficiency in SystemVerilog and UVM-based verification environments.
Strong debugging skills including waveform analysis, coverage review, and simulation log interpretation.
Experience with power analysis tools such as PrimeTime PX and VCD generation.
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
Ability to work in English across global teams.

Yêu cầu ưu tiên

Mức lương

The recruiter will provide more details about the salary range during the hiring process.

Phúc lợi

Thông tin khác

Work on PHY IP for memory and interconnect infrastructure used in AI, data centers, and next-generation compute.

ASIC Digital Design, Sr Staff Engineer