SoC Verification Engineer
TP. Hồ Chí Minh
Hạn nộp hồ sơ:
11/11/2026
Về công việc
Trách nhiệm chính
- Define block and subsystem verification plans that map directly to design specifications and protocol requirements
- Build UVM testbenches in System Verilog, including agents, scoreboards, coverage models, and assertion monitors
- Write constrained random and directed tests that exercise protocol compliance, corner cases, and error injection scenarios
- Debug RTL and testbench failures using simulators and waveform analysis to root cause and resolve issues
- Collaborate with RTL designers and global verification engineers to align on design intent and coverage goals
- Apply formal verification techniques to prove properties and close coverage gaps
- Drive verification closure by tracking coverage metrics and iterating on test plans until signoff
Yêu cầu
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science or related fields
- 0-4 years of hands‑on design verification experience in the semiconductor industry
- Proficiency in System Verilog and UVM for building testbenches and implementing coverage
- Knowledge of at least one protocol such as AMBA, PCI Express, CXL, UCIe, Ethernet, HBM, or DDR
- Experience with industry standard simulators like VCS, Xcelium, or Questa, and version control systems
- Solid scripting skills in Python, Perl, or Tcl for automation and regression management
Thông tin khác
- Remote eligible: No
- Team located in Ho Chi Minh City, District 7
- Synopsys promotes inclusion and diversity for all applicants
Việc làm liên quan
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Officehaus Building,32 Bo Bao Tan Thang,Tan Son Nhi Ward
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TP. Hồ Chí Minh
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