Design Verification Intern
Đà Nẵng
Hạn nộp hồ sơ:
07/11/2026
Về công việc
Trách nhiệm chính
- Read and understand design specifications, and help create test plans and coverage plans.
- Study the existing coverage group definitions and test cases, then write new tests, including constrained-random tests, to improve coverage.
- Run simulations, understand how the block under test operates, and debug failures.
- Work toward coverage improvement and closure.
- Contribute to improvements in the DV strategy, flow, and scripts.
- Collaborate with design engineers to resolve issues, and document your verification results.
Yêu cầu
- Currently pursuing a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Electrical & Computer Engineering (expected to graduate in 2027 or 2028).
- Familiar with Verilog and SystemVerilog.
- Good English.
- Strong debugging and problem‑solving skills, and the ability to work well in a team.
Yêu cầu ưu tiên
- Knowledge of UVM.
- Experience with scripting languages such as Python or Perl, and a Linux working environment.
- Understanding of digital design fundamentals and mixed‑signal design concepts.
Thông tin khác
- Internship position at Marvell Technology in Đà Nẵng, Vietnam.
- Full‑time internship.
- No salary information provided.
- No application deadline specified.
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