Design For Test, Technical Manager
Application deadline:
18/11/2026
About This Job
Trách nhiệm chính
- Work with multi-functional global teams to design, implement and verify hardware DFT features, including Boundary Scan, Internal SCAN with compression, ATPG (Stuck-at/Atspeed), MBIST, and JTAG/IJTAG circuitry.
- Responsible for development of innovative DFT IP in collaboration with the cross-functional teams, and play a key role in full chip design integration with the testability features integrated in RTL or gate-level netlist.
- Work independently to generate test plans, run simulations and debug failures on DFT circuit.
- Work closely with the RTL design/Design verification and Physical design teams to enable the integration and validation of test logic in all phases of the design.
- Work in close collaboration with test engineering team to deliver ATE patterns and support post silicon bring-up debugging.
Yêu cầu
- 10+ years of DFT engineering experience.
- Experience in leading a team and training new member in the overall process.
- Strong DFT & leadership skills.
- Be able to work on two or more projects simultaneously.
- Strong support for team members.
- Strong proficiency in English.
Thông tin khác
- Quest Global is a leading engineering services provider with over 25 years of experience.
- Quest Global values diversity, inclusion, and a culture of respect where everyone belongs, is valued, and feels inspired to share ideas.
- Quest Global’s teams regularly invest time and dedicated effort into internal culture work, ensuring that all voices are heard.
- Quest Global fosters a culture rooted in respect, where everyone belongs, is valued, and feels inspired to share ideas.