Design For Test, Senior/ Lead Engineer
Application deadline:
18/11/2026
About This Job
Trách nhiệm chính
- Conduct DFT engineering tasks: DFT audit/scan logic/MBIST logic/BSCAN logic insertion.
- Implement hardware DFT features supporting ATE, in-system test, debug and diagnostics.
- Develop innovative DFT IP with cross-functional teams and play a key role in full chip design integration with testability features in RTL.
- Work closely with design, verification and physical design teams to enable integration and validation of test logic in all design phases and back-end implementation flow.
- Analyze timing reports and suggest solutions.
- Perform gate-level simulations with and without timing annotations.
- Diagnose and analyze data logs during silicon bring-up to finalize prototype patterns.
- Lead innovative hardware DFT for new silicon device models, bare die & stacked die, reusable test and debug strategies.
Yêu cầu
- 4+ years of DFT engineering experience.
- Strong understanding of scan and compression (EDT) design at top and block level.
- Familiar with OCC architecture for stuck-at/transition modes.
- Good knowledge of MBIST, BIRA, and BISR.
- Strong experience in analyzing ATPG fault lists to achieve high test coverage.
- Experience in gate-level simulations with and without timing annotations.
- Knowledge of Verilog HDL and experience with simulators and waveform debugging tools.
- Understanding of DV methodologies for validating DFT implementation in simulation pre-silicon.
- Familiar with programming languages: Shell, Perl, Tcl.
- Experience in EDA DFT tools.
- Good scripting skills and ability to design and debug with minimal oversight.
Thông tin khác
- Quest Global is a leading engineering services provider with over 25 years of experience, fostering a culture of diversity, respect, and innovation.